1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) including a sequence circuit, such as a shift register circuit, arbitrate circuit or flip-flop circuit, where output is not determined merely by the present input alone and is dependent also on the past hysteresis. More particularly, the invention relates to an arbitrate circuit for sequentially giving proper priority to a plurality of request signals upon occurrence of competitive input of various request signals such as access requests, refresh requests and so forth. And it further relates to a pulse generator circuit for generating, in an IC including a sequence circuit such as an arbitrate circuit, a reset pulse to initialize the sequence circuit at the time of switching on a power source or in response to recovery from a momentary power interruption.
2. Description of the Prior Art
In the conventional semiconductor memory units, there is known a type having two ports as shown in FIG. 9. This exemplary memory unit includes a memory core 91 and is accessible selectively after access requests are outputted respectively from the ports A and B. And when a timing coincidence happens to occur between such access requests, an arbitrate circuit 92 serves to give priority to one access while suspending the other.
FIG. 10 shows the constitution of a conventional arbitrate circuit as a known example. The arbitrate circuit 92 comprises two 2-input AND circuits 93 and 94, wherein each output signal thereof is inverted and fed to one input of the other AND circuit mutually while the remaining inputs receive access requests from the ports A and B respectively, and the individual outputs serve to control the transfer between the ports A, B and the memory core 91.
Describing the operation of such an arbitrate circuit 92 briefly, it is assumed now that initially there exists access requests from the two ports A and B, and both the input and output terminals of the AND circuits 93 and 94 are at a low (L) level. When an access request is received from the port A, the input of the AND circuit 93 is turned to a high (H) level so that the output thereof is changed to a high level. As a result, signal transfer between the port A and the memory core 91 is rendered possible. Meanwhile the output of the AND circuit 93 is inverted and fed to the AND circuit 94. Therefore the output of the AND circuit 94 is turned to a low level, which is kept in such a state despite the arrival of any access request from the port B. That is, the access request from the port B is not accepted unless the preceding access request from the port A is halted.
Although the above-described arbitrate circuit 92 is a type with two ports, the recent further diversity of the memory unit tends to necessitate enhanced arbitration of request signals from 3 or more ports.
However, in the known constitution where gate circuits are arranged in parallel correspondingly to the number of ports and any other gate circuits are merely closed in response to the arrival of a signal from one port, there arises a problem upon the occurrence of competitive input of second, third and following access requests. Suppose here that, during the execution of an access according to a first access request received from one port, a next or second access request is inputted and further a third access request is received. Then, since no priority order is given with regard to the second and third access request signals, there occurs a competitive process at the completion of the first access to eventually fail in achieving the desired arbitration of such signals.
Furthermore, in a sequence circuit such as an arbitrate circuit, shift register circuit, flip-flop circuit or the like whose output is not determined merely by the present input alone and is dependent also on the past hysteresis, the state thereof is rendered unstable at the time of switching on a power source or by any abnormal supply voltage drop caused even for a short time such as momentary power interruption. It is therefore necessary to initialize the sequence circuits in the LSI at the time of switching on the power source or upon receovery from such a momentary power interruption, hence inducing the requirement of a reset pulse generator circuit.
An LSI includes, as shown in FIG. 17 for example, an SR flip-flop consisting of NAND gates 131 and 132. The state of a sequence circuit composed of such an SR flip-flop is not established at the power switch-on time. The SR flip-flop is reset by a reset pulse fed to its reset terminal R.
For attaining the initial state of such SR flip-flop at the power switch-on time, there is provided an external reset pulse generator circuit to output a reset pulse RST as shown in FIG. 18B.
In this external reset pulse generator circuit, a reset pulse RST shown in FIG. 18B is outputted at an instant t.sub.11 upon the increase of the supply voltage V.sub.DD to a predetermined voltage V.sub.11. Such a reset pulse RST is fed to the reset terminal R of the SR flip-flop consisting of NAND gates 131 and 132, whereby the SR flip-flop is reset.
The state of the SR flip-flop in the LSI is unstable at an instant t.sub.10 of the power switch-on time, as shown in FIG. 18C. However, the SR flip-flop is reset at an instant t.sub.11 when such reset pulse RST is outputted, as shown in FIG. 18C.
In the SR flip-flop of FIG. 17 where the reset terminal R thereof is led out, it is resettable by an external reset pulse generator circuit. However, in another flip-flop of FIG. 19 where the output terminal of an inverter 141 is connected to the input terminal of an inverter 142 whose output terminal is connected to the input terminal of the inverter 141, there is not provided any reset terminal so that the flip-flop is not resettable by an external reset pulse generator circuit. Therefore it becomes necessary to incorporate a reset pulse generator circuit in the LSI.
It has been generally customary heretofore that the reset pulse generator circuit incorporated in the LSI is so constituted as shown in FIG. 20.
In FIG. 20, one end of a resistor 151 and one end of a capacitor 152 are connected to each other, and the other end of the resistor 151 is connected to a power supply terminal 153. Meanwhile the other end of the capacitor 152 is connected to a ground terminal 154. The junction of one end of the resistor 151 and that of the capacitor 152 is connected to an input terminal of an inverter 155, whose output terminal is connected to an input terminal of another inverter 156. And the output terminal of the inverter 156 is connected to an output terminal 157 of the reset pulse generator circuit.
A supply voltage V.sub.DD is applied to the power supply terminal 153. In a steady state, the supply voltage V.sub.DD has a value V.sub.21 (e.g. 5 volts) as shown in FIG. 21. When the power source is switched on at an instant t.sub.20, as shown in FIG. 21, the supply voltage V.sub.DD increases from 0 volt to the steady-state voltage V.sub.21 in conformity with the time constant of the power circuit.
With such rise of the supply voltage V.sub.DD, the capacitor 152 is charged by the current flowing in the resistor 151, so that the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 increases with a delay, from the change caused in the supply voltage V.sub.DD, in accordance with the time constant C.sub.152.R.sub.151 determined by the resistance R.sub.151 of the resistor 151 and the capacitance C.sub.152 of the capacitor 152.
The voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 is taken out via inverters 155 and 156. When the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 has exceeded the threshold voltage V.sub.th of the inverter 155, as shown in FIG. 21, the output V.sub.N12 of the inverter 155 is turned to a low level while the output V.sub.N13 of the inverter 156 is turned to a high level. Then the output V.sub.N13 of the inverter 156 is obtained from the output terminal 157 so as to be used as a reset pulse.
Thus, the conventional reset pulse generator circuit incorporated in an LSI is so constituted that the capacitor 152 is charged by the current flowing via the resistor 151, and the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 is changed with a delay from the change caused in the supply voltage V.sub.DD, and a reset pulse is outputted when the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 has exceeded a predetermined threshold value.
However, in such conventional reset pulse generator circuit, the time constant of an integrator consisting of the resistor 151 and the capacitor 152 needs to be greater than that of the power circuit. To the contrary, in case the time constant of the power circuit is greater than that of the integrator consisting of the resistor 151 and the capacitor 152, there arises a problem that a reset pulse is outputted before sufficient rise of the supply voltage V.sub.DD.
If the time constant of the power circuit for supplying required power to the LSI is greater than the time constant of the integrator consisting of the resistor 151 and the capacitor 152, when the power source is switched on at an instant t.sub.30 in FIG. 22, the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 is changed substantially simultaneously with the change in the supply voltage V.sub.DD. As a result, the output of the inverter 155 is turned to a low level at an instant t.sub.31 where the supply voltage V.sub.DD has not risen to a sufficiently high voltage, so that the output of the inverter 156 is turned to a high level to consequently reset the sequence circuit in the LSI.
Thus, in the case that the time constant of the power circuit is greater than that of the integrator consisting of the resistor 151 and the capacitor 152, the change in the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 becomes substantially simultaneous with the change in the supply voltage V.sub.DD, so that there arises a problem of generating a reset pulse before a complete increase of the supply voltage V.sub.DD.
In view of the above problem, there may be contrived a means of selecting, as compared with the time constant of the power circuit, a sufficiently greater time constant of the integrator which consists of the resistor 151 and the capacitor 152. However, some limits are practically existent with regard to the resistance of the resistor and the capacitance of the capacitor attainable in the LSI. Accordingly, in case the integrator is composed of a resistor 151 and a capacitor 152 in the LSI, it is impossible to select a sufficiently great time constant of the integrator consisting of the resistor 151 and the capacitor 152.
Therefore, in attaining selection of a sufficiently great time constant relative to the integrator of the resistor 151 and the capacitor 152, it becomes necessary to provide the resistor 151 and the capacitor 152 externally. However, such external provision of the resistor 151 and the capacitor 152 brings about another problem of increasing the circuit scale.
Besides the above, in the case that the time constant of the integrator consisting of the resistor 151 and the capacitor 152 is selected to be greater than that of the power circuit for supplying required power to the LSI, a further problem arises that the sequence circuit in the LSI is not resettable upon restoration of the normal power supply after any momentary power interruption.
That is, when a momentary power interruption occurs at an instant t.sub.41 in FIG. 23, the supply voltage V.sub.DD drops in conformity with the time constant of the power circuit and finally becomes 0 volt at an instant t.sub.42. Since the state of the sequence circuit in the LSI is thus unstable after occurrence of such momentary power interruption, the sequence circuit needs to be reset posterior to restoration of the normal power supply.
Upon occurrence of a momentary power interruption, the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 is changed very gently as shown in FIG. 23 if the time constant thereof is sufficiently great.
And after such momentary power interruption, the normal power supply is restored at an instant t.sub.43 before the voltage V.sub.N11 at the junction of the resistor 151 and the capacitor 152 drops to a predetermined value. Consequently, no change is caused in the output voltage V.sub.N12 of the inverter 155 or the output voltage V.sub.N13 of the inverter 156 either, whereby the sequence circuit in the LSI fails to be reset after restoration of the normal power supply.